Search - vhdl ram

[File Format] ram_da

Description: 将AD转换得到的八位数据存入RAM，存1000个点，然后通过串行DA读出，DA芯片为TLV5638,AD芯片为tlc0820ac，RAM为FM25L16-AD conversion will be the eight data into RAM, keep 1000 points, and then read out through the DA serial, DA chips for the TLV5638, AD chips for tlc0820ac, RAM for FM25L16
Platform: | Size: 650240 | Author: 王力 | Hits:

[Embeded-SCM Develop] testram_1

Description: EDA实验--RAM实验:利用-MegaWizard Plug-In Manager创建一个16×8的RAM，通过编程对RAM进行读写并在显示器上显示。本例使用三个按键PSW3，PSW2，PSW1，分别对应顶层文件中的x，y，we，we＝1对RAM写，xy＝11时，写入10101011；当xy＝01时，写入01010101；当xy＝10时，写入10101010。we＝0时，对RAM读出。三个按键按下时为0，当PSW1健按下时对RAM进行读出。 -EDA Experimental RAM experiment: the use-MegaWizard Plug-In Manager to create a 16 × 8 of the RAM, through the programming of the RAM read and write and displayed on the monitor. This example uses three buttons PSW3, PSW2, PSW1, corresponding to top-level document x, y, we, we = 1 on RAM write, xy = 11, the write 10101011 when xy = 01 hours, write 01010101 when xy = 10, the write 10101010. we = 0 when read out of RAM. Press the three keys for 0, when PSW1 Kin-pressed to read out of RAM.
Platform: | Size: 4096 | Author: 黄龙 | Hits:

[Other] ddr_ctrlv

Description: ddr ram controller vhdl code
Platform: | Size: 55296 | Author: heyong | Hits:

[VHDL-FPGA-Verilog] sram+lcd

Description: 用vhdl格式写的sram源代码，把扩展名txt改为.v即可-VHDL format used to write the SRAM source code, to be re-txt extension. V can
Platform: | Size: 2048 | Author: 郭艳红 | Hits:

[VHDL-FPGA-Verilog] uriscram

Description: RAM存储器：设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write= 1 则mem(conv_integer(address))<=datain. -RAM memory: Set 16 8 memory cell. If read = 1 is dataout
Platform: | Size: 1024 | Author: 良芯 | Hits:

[VHDL-FPGA-Verilog] ramvhdllib_06

Description: The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
Platform: | Size: 615424 | Author: cathy | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Platform: | Size: 1031168 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
Platform: | Size: 1013760 | Author: wfs | Hits:

[Software Engineering] 20060510191318991

Description: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Platform: | Size: 2253824 | Author: 盛雪飞 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 存储器模块生成，采用16位数据总线，5位读写地址总线，异步清零！-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
Platform: | Size: 2048 | Author: 齐磊 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。 7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取，数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[VHDL-FPGA-Verilog] pingpangVHDL

Description: 据说是 vhdl的乒乓ram 代码提供给大家做个参考吧 -It is said VHDL code of the ping-pong ram available to the U.S. to be a reference to it
Platform: | Size: 1024 | Author: 白饭 | Hits:

[VHDL-FPGA-Verilog] ram

Description: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Platform: | Size: 1024 | Author: sri | Hits:

[VHDL-FPGA-Verilog] dual_port_ram

Description: 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
Platform: | Size: 274432 | Author: zhangyan | Hits:

[Other] FPGA-TWO-RAM

Description: 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
Platform: | Size: 4096 | Author: zhan | Hits:

[Linux-Unix] DP_RAM_lab

Description: 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger display.
Platform: | Size: 4096 | Author: 劳杰勇 | Hits:

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[File Format] ram_da

[Embeded-SCM Develop] testram_1

[Other] ddr_ctrlv

[VHDL-FPGA-Verilog] sram+lcd

[VHDL-FPGA-Verilog] uriscram

[VHDL-FPGA-Verilog] ramvhdllib_06

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

[Software Engineering] 20060510191318991

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] pingpangVHDL

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] dual_port_ram

[Other] FPGA-TWO-RAM

[Linux-Unix] DP_RAM_lab

[VHDL-FPGA-Verilog] ram_Test

[VHDL-FPGA-Verilog] sj_work

[VHDL-FPGA-Verilog] the_VHDL_programe_of_generate_RAM

[VHDL-FPGA-Verilog] hdl

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